NEWS

4-Bit Manchester Chain Carry-Look Ahead Adder using Domino Logic

My ECE 438 final project was to design and layout a 4-bit adder on the TSMC 180 nm process. This is a dual manchester chain 4-bit adder design using full domino logic aiming for maximum frequency. D Flip-Flops to hold the output and a delayed clock buffer to delay the evaluate of the second XOR are included in the layout. Maximum final operating stable frequency at 1.4 GHz, consuming 2.5 mW on average and 2.2 mm^2 of area-- also capable of scaling down to 500 MHz and consuming 1.1 mW.

CMOS NAND Layout

For my University of Waterloo ECE 438 course, I made my first layout -- the NAND gate! with Cadence Virtuoso using TSMC 180 nm technology -- Voila! The gate can still be optimized a little bit more -- the PMOS and NMOS can be made even a little bit more closer. The NMOS can be also be optimized to be an NPNPN sequence instead of 2x NPN transistors in series. NMOS: 180 nm channel length and 1 100 nm channel width, PMOS: 180 nm channel length and 2 000 nm channel width -- achieving a balanced TpHL and TpLH of 80 ps.

Mountain View

I am now working at Google for my fourth internship. I will be working in one of the Linux Kernel teams working on File Systems and disk related research with engineering statistical analysis.

2B Computer Engineering

My internship at Intel has been completed and I am back at the University of Waterloo to complete my degree in Computer Engineering. I am contemplating on switching to the University of Toronto since they appear to have much more resources, they are more research oriented, and they can provide more opportunities.

VLSI

Professor Mohab Anis has just accepted me to be part of his VLSI research team for Fall 2008.

2200 Mission College Blvd.

I just started my internship at Intel in Santa Clara, California. I'll be working for the Mobile Platforms Power and Performance Forecasting Group.

Finally Decided...Going for Intel

CALIFORNIAAAAA HERE I COME! ... (again). After carefully evaluating my options, I've decided to work for Intel (Santa Clara HQ) for my next internship starting at May for 4 months.

New York!

Thank you D.E. Shaw for flying me down to New York for an interview. They have some really crazy and advance research going on over there.

Back to School!

I've completed my internship at NVIDIA. Many thanks to those on my team for giving me a great experience at NVIDIA while having lots of fun at the same time. I am back at Waterloo now entering my 2A study term for Computer Engineering.

Updates

Updated resume and portfolio.

Uploading...

I am slowly uploading some of my works into the portfolio section of the site.

Welcome

Welcome to my personal site. I am currently in my 1B term for BASc. in Computer Engineering at the University of Waterloo. I will be working for NVIDIA in Santa Clara for a 4 month workterm at the end of August.